1. Field of the Invention
Method and apparatus consistent with the present invention relate to transmitting data using direct memory access control.
2. Description of the Related Art
Direct memory access (DMA) control is a method of controlling data stored in a source memory in order for the data to be directly transmitted to a destination memory without passing through a central processing unit (CPU).
In order to use the DMA method, a DMA controlling device needs to be installed on a system bus.
FIG. 1 is a schematic diagram illustrating an operation of a related art DMA controlling apparatus 120. Referring to FIG. 1, a central processing unit (CPU) 110, the DMA controlling apparatus 120, a source memory 130, and a destination memory 140 are connected to a bus 150. The DMA controlling apparatus 120 receives a system controlling authority from the CPU 110 and processes the system controlling functions of the CPU 110. To achieve this, if the system control function is to read or write a data block, for example, the CPU 110 transmits a command for a read/write operation, addresses of the source memory 130 and destination addresses of the destination memory 140, and information about, for example, the amount of data to be transmitted, to the DMA controlling apparatus 120 via the bus 150. After sending the command and the information to the DMA controlling apparatus 120, the CPU 110 performs other operations.
The DMA controlling apparatus 120 controls the data stored in the source memory 130 in order to transmit the data to the destination memory 140 without passing the data through the CPU 110. A control mode of the DMA controlling apparatus 120 when performing the above-described control may be a single mode or a burst mode.
The single mode denotes a mode in which if a high-level interrupt is generated during data transmission to the destination memory 140, the high-level interrupt is processed and the data transmission is then resumed. The burst mode denotes a mode in which transmission of all consecutive data blocks is completed without interruptions. Accordingly, in the single mode, one piece of data is transmitted and received when access permission is granted. In the burst mode, a plurality of data is transmitted and received when access permission is granted.
An operation of the DMA controlling apparatus 120 in the burst mode with reference to FIG. 1 will be described in detail. First, the DMA controlling apparatus 120 transmits to the source memory 130 a signal indicating that the DMA controlling apparatus 120 wants to receive data with a length corresponding to a currently set burst length value. For example, when the burst length value is four words, a signal indicating a desire by the DMA controlling apparatus 120 to transmit data with a length of four words is transmitted to the source memory 130.
In response to the signal from the DMA controlling apparatus 120, the source memory 130 transmits data with a length of four words from among the data that is to be transmitted to the DMA controlling apparatus 120. The DMA apparatus 120 stores the data with a length of four words received from the source memory 130 in a First In First Out (FIFO) memory included in the DMA apparatus 120.
Then, the DMA apparatus 120 transmits to the destination memory 140 a signal indicating a transmission of data with a length of four words, and then transmits the data with a length of four words to the destination memory 140. This transmission process repeats until all of the data stored in the source memory 130 is transmitted to the destination memory 140.
FIG. 2 is a schematic diagram illustrating a data transmission performed by the related art DMA controlling apparatus 120 of FIG. 1. The data transmission illustrated in FIG. 2 is performed when a burst length value is four words and remaining data corresponding to the data remaining in the source memory 130 after repetition of four-word-unit transmissions is six words.
Referring to FIG. 2, in period 210, data corresponding to six words is stored in the source memory 130 before data transmission starts, and the burst length value is set to be four words.
In period 220, four-word data corresponding to the burst length value from among the six-word data remaining in the source memory 130 is transmitted to the destination memory 140, and thus two-word data remains in the source memory 130. Since the burst length value is fixed at four words, the remaining two-word data cannot be transmitted in a burst mode.
In period 230, after the CPU 110 changes the burst mode to a single mode, data corresponding to one word from among the remaining two-word data is transmitted.
In period 240, one-word data remaining in the source memory 130 is transmitted to the destination memory 140 after period 230. Therefore, the transmission of all of the data stored in the source memory 130 is completed.
As described above, in a conventional DMA controlling method, a burst length value is fixed in a burst mode, and thus, data with a length smaller than the fixed burst length value must be transmitted in a single mode. Thus, a CPU must perform an additional operation of changing a mode to transmit the remaining data in the single mode. Moreover, except when a chip is initially designed, there is no way to check the transmission efficiency during the data transmission. In other words, only in the operation of initially designing a chip, the transmission efficiency can be checked.